General Summary This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip) designed by Qualcomm. The engineer will be responsible for characterization and developing cost‑effective manufacturing test solutions for HSIO (SERDES) for leading‑edge SoC products in the most advanced processes. These include but are not limited to HSIO PHY testing with automated test equipment (ATE). Main responsibilities include defining and executing the development of test methodologies and characterization of high‑speed SERDES interfaces such as PCIe, USB3, UFS, DP, and MIPI (DSI, CSI). The engineer will develop characterization and test plans, identify DFT and test hardware requirements, and develop ATE tests/routines/programs to execute test plans. The engineer will drive first silicon debug to qualify designs fabricated at external foundries, perform technical data analysis of parametric performance over various operating conditions and configurations, drive failure analysis to completion, analyze high‑volume manufacturing yields, and drive test time reduction. The engineer will work with cross‑functional teams such as IC Design, Systems Engineering, Process Engineering, Hardware Applications, and Customer Engineering across the globe in a time‑critical environment, driving improvements in the yield, test time, and quality. The individual selected should be passionate about delivering quality work products, continually learn about Qualcomm products, understand industry trends and competitor products, and assist in conducting specialized analyses (e.g., feasibility studies, signal integrity, teardown analyses). Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Qualifications Master's degree in Electrical or Computer Engineering or related field. 3-5 years of hardware engineering experience in related areas. Knowledge of VLSI, CMOS analog, digital, mixed‑signal, and semiconductor physics. Knowledge of HSIO PHY testing is a plus (e.g., SERDES characterization/validation, loopback, compliance test on PHYs such as PCIe, UFS, USB2/3/4, MIPI CSI/DSI). Good ASIC device‑level characterization skills. System‑level knowledge is a plus. Knowledge of Advantest 93K test platform is a plus. Knowledge of signal integrity is a plus. Knowledge of computer programming fundamentals (C/C++/Java/Perl). Knowledge in test automation development/scripting/debugging is a plus. Strong interpersonal, verbal, and written communication skills as well as organization and documentation skills. Strong problem‑solving & debugging skills. Ability to work independently and with good initiative to overcome technical challenges. EEO Statement Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑ or call Qualcomm's toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. #J-18808-Ljbffr