Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description For more than 45 years, Micron Technology, Inc. has transformed innovation with the world’s most advanced memory and semiconductor technologies. We are looking for a Layout Design engineer at our Micron Technology’s HBM Team in Guadalajara, Mexico. As a Layout Design engineer, you will be working on intensive applications such as artificial intelligence and high performance computing solutions, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams across Micron’s global footprint in a multiple project-based environment. Responsibilities Design and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environments. Effectively communicate with Global engineering teams to assure the success of the layout project. Minimum Qualifications Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET). BE or MTech in Electronic/VLSI Engineering, or related. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Hands‑on experience creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. Knowledge of Analog Layout fundamentals (e.g., Matching, Electro‑migration, Latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices). Understanding how layout effects on the circuit such as speed, capacitance, power and area. Ability to understand design constraints and implement high‑quality layouts. Preferred Qualifications Multiple tape‑out support experience will be an added advantage. Experience handling multiple layout projects, ensuring quality checks are considered at all stages of layout development. Excellent command and problem‑solving skills in physical verification of custom layout. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. #J-18808-Ljbffr