Position Overview Layout Design Engineer – HBM Team, Guadalajara, Mexico. Responsibilities Design and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on‑time delivery of block‑level layouts with acceptable quality. Lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple‑project environment. Effectively communicate with Global engineering teams to assure the success of layout project. Minimum Qualifications 5+ years of experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET). BE or MTech in Electronic/VLSI Engineering, or related. Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS is a must. Hands‑on experience creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier. Knowledge of Analog Layout fundamentals (Matching, Electro‑migration, Latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices). Understanding layout effects on the circuit such as speed, capacitance, power and area. Ability to understand design constraints and implement high‑quality layouts. Preferred Qualifications Multiple Tape‑out support experience. Experience managing multiple layout projects and ensuring quality checks at all stages. Excellent command and problem‑solving skills in physical verification of custom layout. Equal‑Opportunity Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. #J-18808-Ljbffr