Job Details: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume, but an English version will be required to be considered. As an Atom CPU Layout Design Engineer, you will be part of a highly skilled team responsible for the design of future‑generation, high‑performance Intel Atom microprocessors. In this role, you will drive the physical implementation of a variety of memory compilers, custom IP blocks, and layout partitions that directly support Intel’s CPU products. Work will be in a dynamic environment where design challenges are complex, assignments broadly defined, and solutions often require creativity, deep technical knowledge, and strong problem‑solving skills. Responsibilities Ensure all physical design implementations follow best‑in‑class layout methodologies and deliver highly efficient, high‑quality results. Independently perform and drive complex physical design assignments across multiple design stages. Work closely with circuit design engineers to interpret schematics and translate them into optimized physical layouts. Contribute across the full design flow—from leaf‑level cell layout to block‑level and top‑level integration. Partner with SoC teams and cross‑site design groups to ensure alignment, reuse, and consistency across projects. Develop or enhance layout scripts, macros, and automation solutions to improve productivity and design robustness. Behavioral Traits Excellent communication and interpersonal skills. Prioritization and multitasking skills. Good analytical and problem‑solving skills. Qualifications Minimum Qualifications Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field. 2+ years of experience in layout design. Advanced English level. Must have unrestricted, permanent right to work in Mexico (no visa or immigration sponsorship). Preferred Qualifications Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline. 2+ years of experience or familiarity with Very Large Scale Integration (VLSI) and Complementary Metal‑Oxide‑Semiconductor (CMOS) logic circuit design. 2+ years of knowledge in Unix/Linux operating systems. Job Type: Experienced Hire. Shift: Shift 1 (Mexico). Primary Location: Mexico, Guadalajara. Additional Locations: Business group: Silicon and Platform Engineering Group (SPE). Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust: N/A. Work Model: This role will require an on‑site presence. #J-18808-Ljbffr