JR Sr Engineer/Layout Engineer, Memory CAD, Guadalajara CAD Engineer4 Relocation Level:TBD Responsibilities Develop, maintain, and support CAD software for product and process development. Build and validate P‑cells, utilities, and automation scripts for layout and verification tasks. Design and support automation for physical design, verification, optimization, and tapeout workflows. Collaborate with PI engineers and design teams to implement effective layout methodologies. Apply understanding of CMOS process fundamentals and design rules in layout work. Minimum Qualifications Bachelor’s or preferably a Master’s/PhD in Computer Engineering, Computer Science, or Electrical Engineering. 5+ years of experience in Design Automation or analog layout. Experience with SKILL, Python, or recent proven experience with C, C++, Java, Visual Basic, Perl, or Lisp. Experience with Unix and shell scripting. Understanding of PDK development, validation, and EDA tool flows. Preferred Qualifications Experience in VLSI circuit design and related software. Proficiency with IC CAD tools for schematics, layout, simulation, and verification. Knowledge of CMOS implementation trade‑offs in area, speed, and power. Experience with Machine Learning algorithms and applications and delivering production‑grade ML applications in IC Design. Benefits Choice of medical, dental, and vision plans. Income protection program for illness or injury. Paid family leave. Robust paid time‑off program. Paid holidays. Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr