Job Details This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position. Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre‑silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, post‑silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post‑silicon on the quality of validation done during pre‑silicon development, updates test plan for missing coverages, and proliferates to future products. Behavioral Traits Collaborating within cross-functional teams to resolve complex technical challenges Analytical and problem‑solving skills with attention to detail Communicate technical concepts effectively to diverse audiences Very good logical thinking, prioritize work and multi‑tasking Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science or a related field with 3+ years of experience in industry‑standard practice or a Master's degree with 2+ years of experience. 2+ years of experience in industry‑standard verification methodologies such as UVM or System Verilog or relevant experience in Silicon Validation. Advanced English language level. Preferred Qualifications 4+ years System Verilog and UVM experience 3+ years in: Python for test automation ARM‑based SoC or equivalent architectures Pre‑silicon verification experience C/C++ and scripting proficiency (Perl, Tcl, Shell) Tools and Verification: 2+ years with simulation tools (VCS, Xcelium, Questa) Formal verification tools and coverage analysis Constrained random and assertion‑based verification AMBA protocols (AXI, AHB, APB) and interconnects Memory subsystems, cache coherency, power management High‑speed interfaces (PCIe, DDR, USB, Ethernet) Linux/Unix and version control (Git, Perforce) Regression testing and CI/CD pipelines Security verification methodologies Experience in some or all aspects of pre‑silicon functional verification, including planning, debug, testbench design, UPF and coverage closure Job Type Experienced Hire Shift Shift 1 (Mexico) Primary Location Mexico, Guadalajara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr