Job Title JR – DRAM Design Tech Layout Engineer Position Level: Layout/Mask Designer E3 – Relocation Level: TBD Responsibilities Design and develop IP layouts used in DRAM chips. Perform layout verification (LVS/DRC/EM), quality check and documentation. Deliver block‑level layouts on time with acceptable quality. Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and breakthroughs in a multi‑project environment. Guide and lead team members in the execution of sub‑block layouts and review their work. Contribute to effective project management. Plan and detail layouts, presenting material for global teams to review. Collaborate with engineering teams in India, Japan, the US, and other global teams to ensure layout project success. Minimum Qualifications BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; exceptionally talented Diploma holders in electronic or VLSI engineering may also be considered. 3+ years of experience in layout design using advanced CMOS processes. Experience with IP layout development and physical verification for complex designs as specified. Expertise in layout area and routing optimization, design rules, yield, and reliability issues. Strong understanding of layout fundamentals: electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, parasitic analysis, matching, shielding, etc. Knowledge of schematics and ability to collaborate with circuit designers and CAD teams. Understanding of layout effects on circuit performance, capacitance, power, area, etc. Excellent problem‑solving skills for area, power, performance, and physical verification of custom layouts. Experience with Cadence tools (Virtuoso schematic editor, Virtuoso layout L, XL, and verification tools such as Mentor Calibre); proficiency in device matching, parasitic analysis, electron migration, and isolation techniques. Leadership qualities and ability to multitask as required. Team‑player with ability to guide and provide technical support to fellow team members. Preferred Qualifications Knowledge of skill coding and layout automation. Self‑motivation, hard work, goal orientation, and excellent verbal & written communication skills. Benefits Micron provides a comprehensive benefits package that includes medical, dental, and vision plans available at all locations. Employees may choose plans that best fit their family’s healthcare needs and budget. Additional programs protect income from illness or injury and offer paid family leave, paid time‑off, and holidays. Equal Opportunity Employment Micron is proud to be an equal‑opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr
Dram Design Tech Layout Engineer
MICRON TECHNOLOGY, INC
tlaquepaque, tlaquepaque
Publicado hace 7 días
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