Responsibilities Responsible for a team to design and develop critical analog, mixed‑signal, custom digital block and full chip level integration support. Manage a team to perform layout verification like LVS/DRC/antenna, quality check and documentation. Ensure on‑time delivery of block‑level layouts with acceptable quality. Coordinate and lead planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environments. Guide junior and senior team members in their execution of sub‑block‑level layouts and review their work. Effectively communicate with global engineering teams to assure the success of layout projects. Minimum Qualifications 10+ years of experience in analog/custom layout design in advanced CMOS processes, across various technology nodes (planar, FinFET). 2+ years of managing, coordinating or leading layout teams. Experience in managing or leading layout teams and projects, ensuring quality checks are taken care of at all stages of layout development. BE or MTech in Electronic/VLSI Engineering, or related field. Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS. Hands‑on experience creating layouts of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc. Knowledge of analog layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices, etc.). Understanding of layout effects on circuit performance such as speed, capacitance, power, and area. Ability to understand design constraints and implement high‑quality layouts. Multiple tape‑out support experience is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. #J-18808-Ljbffr