Company QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area Engineering Group ASICS Engineering General Summary PDK/CAD Engineer - Physical Verification and Extraction Development. In this highly cross‑functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain, and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state‑of‑the‑art tools. You will collaborate with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD), and Chip integration teams to understand their requirements and challenges and to enable flows that meet their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Layout and Programmable ERC, implementing the rules from scratch and/or modifying the existing ones. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Qualifications Expertise in Calibre/ICV/Pegasus runset coding for DRC/LVS/ERC/PERC/MPT/ESD/Latch‑up/Antenna. Experience with developing and customizing the StarRC/Calibre‑xACT/QRC parasitic extraction flows. As a member of the Physical Verification CAD team, maintain and improve all aspects of physical verification flow and methodology. Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules (DRCs), etc. to meet design team requirements. Deep understanding of DRC and LVS runsets, writing from scratch and/or modifying existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other extraction tools. Hands‑on skills to revamp/rewrite and streamline the PEX flow. Understanding of Digital/Custom/Analog requirements for various post‑layout electrical flows. Develop custom extraction solutions for transistor level design team requirements. Hands‑on experience with the Field solvers and RC reduction tools. Support design teams with solving their PEX challenges. Support design teams with solving their PV challenges to facilitate the IP release and chip tapeouts. Collaborate with tool vendor and foundries for tools and flow improvements. Knowledge of deep sub‑micron FINFET, Planar, SOI and PMIC process technologies and mask layout design. Proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL. Good communication skills and ability to work collaboratively in a team environment. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑ or call Qualcomm's toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. #J-18808-Ljbffr