Responsibilities Design and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Will bee leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Effectively communicating with Global engineering teams to assure the success of layout project. Minimum Qualification Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET). BE or MTech in Electronic/VLSI Engineering, or related. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Knowledge of Analog Layout fundamentals (e.g., Matching, Electro‑migration, Latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc. Ability to understand design constraints and implement high‑quality layouts. Preferred Qualifications Multiple Tape out support experience will be an added advantage. Experience handling multiple layout projects, ensuring quality checks are being taken into consideration at all stages of layout development. Excellent command and problem‑solving skills in physical verification of custom layout. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact #J-18808-Ljbffr