Job Title and Location Layout Design Engineer – HBM Team, Guadalajara, Mexico. Responsibilities Design and development of analog, mixed‑signal, custom digital block and full chip level integration support. Perform layout verification such as LVS/DRC/Antenna, quality checks and documentation. Ensure on‑time delivery of block‑level layouts with acceptable quality. Lead planning, area/time estimation, scheduling, delegation and execution to meet project milestones in a multiple‑project environment. Communicate effectively with global engineering teams to ensure successful completion of layout projects. Minimum Qualifications 5+ years of experience in analog/custom layout design in advanced CMOS process across various technology nodes (Planar, FinFET). BE or MTech in Electronic/VLSI Engineering or related field. Proficiency with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS. Hands‑on experience in creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc. Knowledge of analog layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, parasitic devices). Understanding of layout effects on circuit performance (speed, capacitance, power, area). Ability to understand design constraints and implement high‑quality layouts. Preferred Qualifications Experience supporting multiple tape‑outs. Experience managing multiple layout projects while ensuring quality checks at all stages. Excellent command of physical verification of custom layout and strong problem‑solving skills. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. #J-18808-Ljbffr