Define system-level power management architecture and operating modes Define CPU and cluster power states and their coordination mechanisms Define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions Define PM policies, sequencing, and state transitions across the platform Define hardware–firmware power management interfaces and compliance expectations Define power management requirements and constraints to guide implementation teams Align architecture, RTL, physical design, thermal, and firmware teams around a coherent PM strategy Support silicon bring-up and post-silicon power behavior validation Required Experience 7+ years in SoC or CPU power management architecture Direct experience with ARM CPU power management architecture, including familiarity with ARM power management specifications and compliance requirements (e.g., PSCI, ARM power state definitions, firmware coordination models) Strong understanding of system-level power state management and hardware–firmware PM interaction Solid understanding of power delivery constraints Track record of cross-functional coordination across architecture, design, and firmware teams Preferred Experience Familiarity with low-power implementation flows (e.g., UPF) and physical power considerations Understanding of thermal management concepts and power-thermal interaction at system level High-performance or server-class CPU experience RISC-V experience Silicon bring-up and post-silicon tuning experience Multi-generation architecture planning experience Apply for this position Personal information First name Last name Email Address Phone number Nationality Your resume Your LinkedIn Profile Upload your Resume/CV Upload File Max file size 10MB. Upload your coverletter Upload File Max file size 10MB. #J-18808-Ljbffr